; (c) 2024 Sugihara Toshio.
; THERE IS NO WARRANTY FOR THE PROGRAM.
PROCESSOR 12F1822
#include <xc.inc>

; PIC12F1822 Configuration Bit Settings
; CONFIG1
  CONFIG  FOSC = XT             ; Oscillator Selection (XT Oscillator, Crystal/resonator connected between OSC1 and OSC2 pins)
  CONFIG  WDTE = OFF            ; Watchdog Timer Enable (WDT disabled)
  CONFIG  PWRTE = ON            ; Power-up Timer Enable (PWRT enabled)
  CONFIG  MCLRE = ON            ; MCLR Pin Function Select (MCLR/VPP pin function is MCLR)
  CONFIG  CP = OFF              ; Flash Program Memory Code Protection (Program memory code protection is disabled)
  CONFIG  CPD = OFF             ; Data Memory Code Protection (Data memory code protection is disabled)
  CONFIG  BOREN = OFF           ; Brown-out Reset Enable (Brown-out Reset disabled)
  CONFIG  CLKOUTEN = OFF        ; Clock Out Enable (CLKOUT function is disabled. I/O or oscillator function on the CLKOUT pin)
  CONFIG  IESO = OFF            ; Internal/External Switchover (Internal/External Switchover mode is disabled)
  CONFIG  FCMEN = OFF           ; Fail-Safe Clock Monitor Enable (Fail-Safe Clock Monitor is disabled)

; CONFIG2
  CONFIG  WRT = OFF             ; Flash Memory Self-Write Protection (Write protection off)
  CONFIG  PLLEN = ON            ; PLL Enable (4x PLL enabled)
  CONFIG  STVREN = OFF          ; Stack Overflow/Underflow Reset Enable (Stack Overflow or Underflow will not cause a Reset)
  CONFIG  BORV = LO             ; Brown-out Reset Voltage Selection (Brown-out Reset Voltage (Vbor), low trip point selected.)
  CONFIG  DEBUG = OFF           ; In-Circuit Debugger Mode (In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins)
  CONFIG  LVP = ON              ; Low-Voltage Programming Enable (Low-voltage programming enabled)
  
consta	EQU 169
constb	EQU 171
  
; PSECT udata_bank0
; PSECT udata_bank1
PSECT udata_shr
counta:	    ; counter of channel A
    DS	1
countb:	    ; counter of channel B
    DS	1
bufa:	    ; output buffer of PORTA
    DS	1
    
PSECT resetVec,class=CODE,delta=2
resetVec:
    goto    main
    
PSECT intrVec,class=CODE,delta=2
intrVec:
    goto    main
    
main:
    ; Initialize CPU
    clrf    INTCON  ; Disable Interruption
    movlb   0H	    ; Select Bank 0
    movlw   02H
    movwf   bufa
    movwf   PORTA   ; Initialize PORTA (A0=clr, A1=set)
    movlb   2H	    ; Select Bank 2
    movwf   LATA    ; Latch data of PORTA
    movlb   3H	    ; Select Bank 3
    clrf    ANSELA  ; Select Digital I/O
    movlb   1H	    ; Select Bank 1
    movlw   00111000B
    movwf   TRISA   ; Set A0-A2 as output
    movlb   0H	    ; Select Bank 0

    ; Initial wait for about 131ms (525312ops)
    clrf   counta
    clrf   countb
waitloop1:
    nop
    nop
    nop
    nop
    decf    counta, F
    btfss   STATUS, STATUS_ZERO_POSITION
    goto    waitloop1
    nop
    decf    countb, F
    btfss   STATUS, STATUS_ZERO_POSITION
    goto    waitloop1
    nop
    
beepstart:
    movlw   consta
    movwf   counta
    movlw   constb
    movwf   countb

beeploop1:  ; 22 operations time per loop
    decf    counta,F
    btfss   STATUS,STATUS_ZERO_POSITION
    goto    beeploop2
    ; A ch (porta bit0) is time to be changed.
    movlw   01H
    xorwf   bufa,F	; invert A0
    movlw   consta
    movwf   counta	; set counter value again
    goto    beeploop3
    
beeploop2: ; Adjust operation counts
   nop
   nop
   nop
   nop
   nop
   
beeploop3:
    decf    countb,F
    btfss   STATUS,STATUS_ZERO_POSITION
    goto    beeploop4
    ; B ch (porta bit1) is time to be changed.
    movlw   02H
    xorwf   bufa,F	; invert A1
    movlw   constb
    movwf   countb	; set counter value again.
    goto    beeploop5
    
beeploop4: ; Adjust operation counts
   nop
   nop
   nop
   nop
   nop
    
beeploop5:
    movf    bufa,W
    movwf   PORTA	; Update PORTA I/O
    goto    beeploop1
    
END resetVec
    